HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 717

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

16TCNT1H/L⎯Timer Counter 1H/L
GRA1H/L⎯General Register A1 H/L
GRB1H/L⎯General Register B1 H/L
16TCR2⎯Timer Control Register 2
Initial value
Read/Write
Notes: 1. Bit functions are the same as for 16-bit timer channel 0.
Initial value
Read/Write
Initial value
Read/Write
Initial value
Read/Write
Note: Bit functions are the same as for 16-bit timer channel 0.
Note: Bit functions are the same as for 16-bit timer channel 0.
Note: Bit functions are the same as for 16-bit timer channel 0.
2. The settings of bits CKEG1 and CKEG0 and bits TPSC2 to TPSC0 in 16TCR2 are invalid when phase
Bit
counting mode is selected for channel 2.
Bit
Bit
Bit
R/W
R/W
R/W
15
15
15
0
1
1
⎯
⎯
7
1
R/W
R/W
R/W
14
14
14
0
1
1
R/W
R/W
R/W
CCLR1
13
13
13
0
1
1
R/W
6
0
R/W
R/W
R/W
12
12
12
0
1
1
R/W
R/W
R/W
CCLR0
11
11
11
0
1
1
R/W
5
0
R/W
R/W
R/W
10
10
10
0
1
1
R/W
R/W
R/W
CKEG1
9
0
9
1
9
1
R/W
4
0
R/W
R/W
R/W
0
1
1
8
8
8
H'FFF72
H'FFF73
H'FFF74
H'FFF75
H'FFF76
H'FFF77
H'FFF78
R/W
R/W
R/W
CKEG0
7
7
7
Rev.5.00 Sep. 12, 2007 Page 687 of 764
0
1
1
R/W
3
0
R/W
R/W
R/W
6
0
6
1
6
1
Appendix B Internal I/O Registers
R/W
R/W
R/W
5
5
5
0
1
1
TPSC2
R/W
0
2
R/W
R/W
R/W
4
0
4
1
4
1
16-Bit Timer Channel 1
16-Bit Timer Channel 1
16-Bit Timer Channel 1
16-Bit Timer Channel 2
R/W
R/W
R/W
0
1
1
3
3
3
TPSC1
R/W
REJ09B0396-0500
0
1
R/W
R/W
R/W
2
0
2
1
2
1
R/W
R/W
R/W
1
1
1
0
1
1
TPSC0
R/W
0
R/W
R/W
R/W
0
0
0
0
1
0
1