HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 403

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow
signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in
this case.
10.4.5
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit count mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). In this case, the timer operates as below. Similarly, if bits CKS2 to
CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are
cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit count
mode), or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match
count mode). Timer operation in these cases is described below.
16-Bit Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
⎯ Setting when Compare Match Occurs
• The CMF flag is set to 1 in 8TCR0 when a 16-bit compare match occurs.
• The CMF flag is set to 1 in 8TCR1 when a lower 8-bit compare match occurs.
• TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
• TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
Operation with Cascaded Connection
accordance with the 16-bit compare match conditions.
accordance with the lower 8-bit compare match conditions.
Overflow signal
8TCNT
OVF
φ
Figure 10.16 Timing of OVF Setting
H'FF
Rev.5.00 Sep. 12, 2007 Page 373 of 764
H'00
REJ09B0396-0500
10. 8-Bit Timers