HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 19

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.2
5.3
5.4
5.5
Section 6 Bus Controller
6.1
6.2
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 82
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 92
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 97
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 104
5.5.1
5.5.2
5.5.3
Overview........................................................................................................................... 107
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 112
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 128
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 129
Block Diagram ..................................................................................................... 80
Pin Configuration................................................................................................. 81
Register Configuration......................................................................................... 81
System Control Register (SYSCR) ...................................................................... 82
Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 83
IRQ Status Register (ISR).................................................................................... 89
IRQ Enable Register (IER) .................................................................................. 90
IRQ Sense Control Register (ISCR) .................................................................... 91
External Interrupts ............................................................................................... 92
Internal Interrupts................................................................................................. 93
Interrupt Vector Table.......................................................................................... 93
Interrupt Handling Process................................................................................... 97
Interrupt Sequence ............................................................................................... 102
Interrupt Response Time...................................................................................... 103
Contention between Interrupt and Interrupt-Disabling Instruction ...................... 104
Instructions that Inhibit Interrupts........................................................................ 105
Interrupts during EEPMOV Instruction Execution .............................................. 105
Features................................................................................................................ 107
Block Diagram ..................................................................................................... 108
Pin Configuration................................................................................................. 110
Register Configuration......................................................................................... 111
Bus Width Control Register (ABWCR)............................................................... 112
Access State Control Register (ASTCR) ............................................................. 113
Wait Control Registers H and L (WCRH, WCRL).............................................. 113
Bus Release Control Register (BRCR) ................................................................ 117
Bus Control Register (BCR) ................................................................................ 119
Chip Select Control Register (CSCR).................................................................. 121
DRAM Control Register A (DRCRA) ................................................................. 122
DRAM Control Register B (DRCRB) ................................................................. 124
Refresh Timer Control/Status Register (RTMCSR) ............................................ 127
.................................................................................................... 107
Rev.5.00 Sep. 12, 2007 Page xvii of xxviii
REJ09B0396-0500