HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 381
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Manufacturer
Quantity
Price
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10.1
The H8/3006 and H8/3007 have a built-in 8-bit timer module with four channels (TMR0, TMR1,
TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT)
and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the
8TCNT value to detect compare match events. The timers can be used as multifunctional timers in
a variety of applications, including the generation of a rectangular-wave output with an arbitrary
duty cycle.
10.1.1
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
• Selection of three ways to clear the counters
• Timer output controlled by two compare match signals
• A/D converter can be activated by a compare match
• Two channels can be cascaded
• Input capture function can be set
• Twelve interrupt sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input (enabling use as an external event counter).
The counters can be cleared on compare match A or B, or input capture B.
The timer output signal in each channel is controlled by two independent compare match
signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM
output.
⎯ Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit
⎯ Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit
⎯ Channel 1 can count channel 0 compare match events (compare match count mode).
⎯ Channel 3 can count channel 2 compare match events (compare match count mode).
8-bit or 16-bit input capture operation is available.
There are twelve interrupt sources: four compare match sources, four compare match/input
capture sources, four overflow sources.
count mode).
count mode).
Overview
Features
Section 10 8-Bit Timers
Rev.5.00 Sep. 12, 2007 Page 351 of 764
REJ09B0396-0500
10. 8-Bit Timers
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