HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 228
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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7. DMA Controller
7.3
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 7.4.
7.3.1
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.)
Bit
Initial value
Read/Write
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
7.3.2
The I/O address registers (IOARs) are not used in full address mode.
Rev.5.00 Sep. 12, 2007 Page 198 of 764
REJ09B0396-0500
31
⎯
1
Memory Address Registers (MAR)
Register Descriptions (2) (Full Address Mode)
I/O Address Registers (IOAR)
30
⎯
1
29
⎯
1
MARR
28
⎯
1
27
⎯
1
26
⎯
1
25
⎯
1
24
⎯
1
R/W
23
R/W
22
R/W
21
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
Undetermined
R/W
17
R/W
16
R/W
15
R/W
14
R/W
13
R/W
MARH
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
MARL
4
R/W
3
R/W
2
R/W
1
R/W
0
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