HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 456

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface
• Full-duplex communication
• The following settings can be made for the serial data to be transferred:
• Built-in baud rate generator with selectable bit rates
• Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
• Four types of interrupts
Features of the smart card interface are listed below.
• Asynchronous communication
• Built-in baud rate generator with selectable bit rates
• Three types of interrupts
Rev.5.00 Sep. 12, 2007 Page 426 of 764
REJ09B0396-0500
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate with
other chips having a synchronous communication function.
There is a single serial data communication format.
⎯ Data length:
⎯ Receive error detection: overrun errors
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
⎯ LSB-first or MSB-first transfer
⎯ Inversion of data logic level
clock from the SCK pin
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can
activate the DMA controller (DMAC) to transfer data.
⎯ Data length: 8 bits
⎯ Parity bits generated and checked
⎯ Error signal output in receive mode (parity error)
⎯ Error signal detect and automatic data retransmit in transmit mode
⎯ Supports both direct convention and inverse convention
Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA
controller (DMAC) to transfer data.
8 bits