HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 255

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 7.12 shows a sample setup procedure for block transfer mode.
Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.
Set destination address
Set block transfer count
Block transfer mode
Block transfer mode
Set source address
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Set DTCRB (1)
Set DTCRA (1)
Set DTCRB (2)
Set DTCRA (2)
Set block size
Read DTCRB
Read DTCRA
Figure 7.12 Block Transfer Mode Setup Procedure (Example)
1
2
3
4
5
6
7
8
9
10
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Set the source address in MARA.
Set the destination address in MARB.
Set the block transfer count in ETCRB.
Set the block size (number of bytes or words)
in both ETCRAH and ETCRAL.
Set the DTCRB bits as follows.
•
•
•
•
Set the DTCRA bits as follows.
•
•
•
•
•
Read DTCRB with DTME cleared to 0.
Set the DTME bit to 1 in DTCRB.
Read DTCRA with DTE cleared to 0.
Set the DTE bit to 1 in DTCRA to enable
the transfer.
Clear the DTME bit to 0.
Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
Set or clear the TMS bit to make the block area
the source or destination.
Select the DMAC activation source with bits
DTS2B to DTS0B.
Clear the DTE to 0.
Select byte size or word size with the DTSZ bit.
Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
Set bits DTS2A to DTS0A all to 1 to select
block transfer mode.
Rev.5.00 Sep. 12, 2007 Page 225 of 764
7. DMA Controller
REJ09B0396-0500