HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 541

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

• Retransmission when SCI is in Transmit Mode
6. If an error signal is sent back from the receiving device after transmission of one frame is
7. The TEND bit in SSR is not set for the frame for which the error signal was received.
8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.
9. If an error signal is not sent back from the receiving device, transmission of one frame,
Note on Block Transfer Mode Support: The smart card interface installed in the H8/3006 and
H8/3007 support an IC card (smart card) interface with provision for ISO/IEC7816-3 T=0
(character transmission). Therefore, block transfer operations are not supported (error signal
transmission, detection, and automatic data retransmission are not performed).
Ds
Figure 14.13 illustrates retransmission when the SCI is in transmit mode.
completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an
ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit
sampling timing.
including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in
SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is
enabled as a DMA transfer activation source, the next data can be written in TDR
automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to
0.
TDRE
TEND
ERS
Transfer from TDR to TSR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Frame n
Figure 14.13 Retransmission in SCI Transmit Mode
[6]
[7]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
Retransmitted frame
Rev.5.00 Sep. 12, 2007 Page 511 of 764
(DE)
[8]
[9]
14. Smart Card Interface
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
Frame n+1
REJ09B0396-0500