HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 580

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

18. Clock Pulse Generator
18.2.2
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
18.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray
capacitance at the XTAL pin exceeds 10 pF, use configuration b instead and hold the clock high in
standby mode.
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 18.3 shows the clock timing, figure 18.6
shows the external clock input timing, and figure 18.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Rev.5.00 Sep. 12, 2007 Page 550 of 764
REJ09B0396-0500
External Clock Input
EXTAL
XTAL
EXTAL
XTAL
Figure 18.5 External Clock Input (Examples)
b. Complementary clock input at XTAL pin
a. XTAL pin left open
DEXT
Open
) has passed after the clock input. The system
DEXT
, while the clock output is unstable.
External clock input
External clock input