HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 24

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.5 Interrupt ............................................................................................................................ 376
10.6 8-Bit Timer Application Example..................................................................................... 377
10.7 Usage Notes ...................................................................................................................... 378
Section 11 Programmable Timing Pattern Controller (TPC)
11.1 Overview........................................................................................................................... 389
11.2 Register Descriptions ........................................................................................................ 393
11.3 Operation .......................................................................................................................... 404
Rev.5.00 Sep. 12, 2007 Page xxii of xxviii
REJ09B0396-0500
10.4.2 Compare Match Timing....................................................................................... 369
10.4.3 Input Capture Signal Timing ............................................................................... 371
10.4.4 Timing of Status Flag Setting .............................................................................. 372
10.4.5 Operation with Cascaded Connection.................................................................. 373
10.4.6 Input Capture Setting ........................................................................................... 375
10.5.1 Interrupt Source ................................................................................................... 376
10.5.2 A/D Converter Activation.................................................................................... 377
10.7.1 Contention between 8TCNT Write and Clear...................................................... 378
10.7.2 Contention between 8TCNT Write and Increment .............................................. 379
10.7.3 Contention between TCOR Write and Compare Match ...................................... 380
10.7.4 Contention between TCOR Read and Input Capture ........................................... 381
10.7.5 Contention between Counter Clearing by Input Capture and
10.7.6 Contention between TCOR Write and Input Capture .......................................... 383
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
10.7.8 Contention between Compare Matches A and B ................................................. 385
10.7.9 8TCNT Operation at Internal Clock Source Switchover ..................................... 385
11.1.1 Features................................................................................................................ 389
11.1.2 Block Diagram..................................................................................................... 390
11.1.3 Pin Configuration................................................................................................. 391
11.1.4 Register Configuration......................................................................................... 392
11.2.1 Port A Data Direction Register (PADDR) ........................................................... 393
11.2.2 Port A Data Register (PADR).............................................................................. 393
11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 394
11.2.4 Port B Data Register (PBDR) .............................................................................. 394
11.2.5 Next Data Register A (NDRA) ............................................................................ 395
11.2.6 Next Data Register B (NDRB)............................................................................. 396
11.2.7 Next Data Enable Register A (NDERA).............................................................. 398
11.2.8 Next Data Enable Register B (NDERB) .............................................................. 399
11.2.9 TPC Output Control Register (TPCR) ................................................................. 400
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 402
Counter Increment ............................................................................................... 382
(Cascaded Connection) ........................................................................................ 384
................................. 389