HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 196

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
6. Bus Controller
• Figure 6.30 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit
Rev.5.00 Sep. 12, 2007 Page 166 of 764
REJ09B0396-0500
organization, and the corresponding address map. The DRAMs used in this example are of the
11-bit row address × 10-bit column address type. The CS2 pin is used as a common RAS
output pin for area 2 and area 3. When the DRAM address space spans a number of contiguous
areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS
pin to be used as the common RAS output pin for a number of areas, and makes it possible to
directly connect large-capacity DRAM with address space that spans a maximum of four areas.
Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports.
Figure 6.30 Interconnections and Address Map for 16-Mbit DRAMs with × 8-Bit
H8/3006 and H8/3007
A21, A10-A1
PB4 (UCAS)
CS2 (RAS2)
PB5 (LCAS)
Area 2
Area 3
Area 4
Area 5
RD (WE)
D15-D8
D7-D0
H'400000
H'5FFFFE
H'600000
H'7FFFFE
H'800000
H'9FFFFE
H'A00000
H'BFFFFE
(a) Interconnections (example)
(UCAS)
15
Organization
(b) Address map
PB4
DRAM
(No.1)
16-Mbyte mode
Normal
Normal
8
7
DRAM
(No.2)
(LCAS)
PB5
11-bit row address × 10-bit column address
0
CS2(RAS2)
CS4
CS5
D7-D0
D7-D0
RAS
CAS
WE
A10-A0
RAS
CAS
WE
A10-A0
2-CAS 16-Mbit DRAM
× 8-bit organization
OE
OE
No.1
No.2

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