HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 27

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

15.3 CPU Interface.................................................................................................................... 522
15.4 Operation........................................................................................................................... 523
15.5 Interrupts ........................................................................................................................... 528
15.6 Usage Notes ...................................................................................................................... 529
Section 16 D/A Converter
16.1 Overview........................................................................................................................... 535
16.2 Register Descriptions ........................................................................................................ 537
16.3 Operation........................................................................................................................... 540
16.4 D/A Output Control .......................................................................................................... 541
Section 17 RAM
17.1 Overview........................................................................................................................... 543
17.2 System Control Register (SYSCR) ................................................................................... 544
17.3 Operation........................................................................................................................... 545
Section 18 Clock Pulse Generator
18.1 Overview........................................................................................................................... 547
18.2 Oscillator Circuit............................................................................................................... 548
18.3 Duty Adjustment Circuit ................................................................................................... 552
18.4 Prescalers .......................................................................................................................... 552
18.5 Frequency Divider............................................................................................................. 552
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 518
15.2.3 A/D Control Register (ADCR) ............................................................................ 520
15.4.1 Single Mode (SCAN = 0)..................................................................................... 523
15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 525
15.4.3 Input Sampling and A/D Conversion Time.......................................................... 527
15.4.4 External Trigger Input Timing ............................................................................. 528
16.1.1 Features................................................................................................................ 535
16.1.2 Block Diagram ..................................................................................................... 536
16.1.3 Pin Configuration................................................................................................. 536
16.1.4 Register Configuration......................................................................................... 537
16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 537
16.2.2 D/A Control Register (DACR) ............................................................................ 538
16.2.3 D/A Standby Control Register (DASTCR) .......................................................... 539
17.1.1 Block Diagram ..................................................................................................... 543
17.1.2 Register Configuration......................................................................................... 544
18.1.1 Block Diagram ..................................................................................................... 547
18.2.1 Connecting a Crystal Resonator........................................................................... 548
18.2.2 External Clock Input ............................................................................................ 550
.................................................................................................................. 543
................................................................................................. 535
.................................................................................. 547
Rev.5.00 Sep. 12, 2007 Page xxv of xxviii
REJ09B0396-0500