HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 256

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7. DMA Controller
7.4.7
The DMAC can be activated by an internal interrupt, external request, or auto-request. The
available activation sources differ depending on the transfer mode and channel as indicated in
table 7.11.
Table 7.11 DMAC Activation Sources
Activation Source
Internal
interrupts
External
requests
Auto-request
Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation
source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible
for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt.
When the DMAC is activated by an interrupt request, the interrupt request flag is cleared
automatically. If the same interrupt is selected to activate two or more channels, the interrupt
request flag is cleared when the highest-priority channel is activated, but the transfer request is
held pending on the other channels in the DMAC, which are activated in their priority order.
Activation by External Request: If an external request (DREQ pin) is selected as an activation
source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output
pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level-
sensitive or edge-sensitive.
Rev.5.00 Sep. 12, 2007 Page 226 of 764
REJ09B0396-0500
DMAC Activation
IMIA0
IMIA1
IMIA2
ADI
TXI0
RXI0
Falling edge
of DREQ
Low input at
DREQ
No
Channels
0A and 1A
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Short Address Mode
Channels
Yes
Yes
Yes
Yes
Yes
Yes
No
0B and 1B
Yes
Yes
Normal
No
No
No
No
No
No
Yes
Yes
Yes
Full Address Mode
Block
Yes
Yes
Yes
Yes
No
No
Yes
No
No