HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 434

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11. Programmable Timing Pattern Controller (TPC)
Bit 0⎯Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP
11.3
11.3.1
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating
conditions.
Rev.5.00 Sep. 12, 2007 Page 404 of 764
REJ09B0396-0500
Bit 0
G0NOV
0
1
TPC output pin
Operation
Overview
3
Description
Normal TPC output in group 0 (output values change at
compare match A in the selected 16-bit timer channel)
Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
to TP
0
).
DDR
Q
Figure 11.2 TPC Output Operation
Q
NDER
Q
DR
C
Output trigger signal
D
Q
NDR
D
(Initial value)
Internal
data bus