HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 525
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Bits 1 and 0⎯Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
0
1
14.3
14.3.1
The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of
• If a parity error is detected during reception, a low error signal level is output for a1 etu period
• If an error signal is detected during transmission, the same data is transmitted automatically
• Only asynchronous communication is supported; there is no synchronous communication
14.3.2
Figure 14.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to V
one bit) is provided between the end of the parity bit and the start of the next frame.
10.5 etu after the start bit.
after the elapse of 2 etu or longer.
function.
Operation
Overview
Pin Connections
Bit 1
CKE1
0
1
Bit 0
CKE0
0
1
0
1
0
1
Description
Internal clock/SCK pin is I/O port
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at low output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at high output
Internal clock/SCK pin is clock output
CC
with a resistor.
Rev.5.00 Sep. 12, 2007 Page 495 of 764
14. Smart Card Interface
REJ09B0396-0500
(Initial value)
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