HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 430

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11. Programmable Timing Pattern Controller (TPC)
11.2.9
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
Initial value
Read/Write
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6⎯Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP
Rev.5.00 Sep. 12, 2007 Page 400 of 764
REJ09B0396-0500
Bit 7
G3CMS1
0
1
TPC Output Control Register (TPCR)
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP
1
Bit 6
G3CMS0
0
1
0
15
G3CMS1
to TP )
R/W
7
1
12
G3CMS0
TPC output group 3 (TP
compare match in 16-bit timer channel 2
Description
TPC output group 3 (TP
timer channel 0
TPC output group 3 (TP
timer channel 1
TPC output group 3 (TP
timer channel 2
R/W
6
1
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP
11
G2CMS1
R/W
to TP )
5
1
8
G2CMS0
R/W
4
1
15
15
15
15
to TP
to TP
to TP
to TP
Group 1 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 1
(TP to TP )
G1CMS1
7
12
12
12
12
R/W
) is triggered by
) is triggered by compare match in 16-bit
) is triggered by compare match in 16-bit
) is triggered by compare match in 16-bit
3
1
4
G1CMS0
R/W
2
1
15
to TP
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP to TP )
G0CMS1
3
12
R/W
).
1
1
0
G0CMS0
(Initial value)
R/W
0
1