HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 165

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
8-Bit Access Areas: Figure 6.5 illustrates data alignment control for 8-bit access space. With 8-bit
access space, the upper data bus (D
can be accessed at one time is one byte: a word access is performed as two byte accesses, and a
longword access, as four byte accesses.
16-Bit Access Areas: Figure 6.6 illustrates data alignment control for 16-bit access areas. With
16-bit access areas, the upper data bus (D
accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Byte size
Word size
Longword size
Byte size
Byte size
Word size
Longword size
Figure 6.6 Access Sizes and Data Alignment Control (16-Bit Access Area)
Figure 6.5 Access Sizes and Data Alignment Control (8-Bit Access Area)
· Even address
· Odd address
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
1st bus cycle
2nd bus cycle
15
to D
8
15
) is always used for accesses. The amount of data that
to D
8
) and lower data bus (D
D
D
15
15
Upper data bus
Upper data bus
Rev.5.00 Sep. 12, 2007 Page 135 of 764
D
D
8
8
D
D
7
7
7
Lower data bus
Lower data bus
to D
0
) are used for
REJ09B0396-0500
6. Bus Controller
D
D
0
0

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