HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 119

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2⎯Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2
0
1
Bit 1⎯Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.
Bit 1
IPRB1
0
1
Bit 0⎯Reserved: This bit can be written and read, but it does not affect interrupt priority.
5.2.3
ISR is an 8-bit readable/writable register that indicates the status of IRQ
requests.
Bit
Initial value
Read/Write
Note:
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can not be modified and are always read as 0.
*
Only 0 can be written, to clear flags.
IRQ Status Register (ISR)
Description
SCI channel 1 interrupt requests have priority level 0 (low priority)
SCI channel 1 interrupt requests have priority level 1 (high priority)
Description
SCI channel 2 interrupt requests have priority level 0 (low priority)
SCI channel 2 interrupt requests have priority level 1 (high priority)
Reserved bits
⎯
⎯
7
0
⎯
⎯
6
0
IRQ5F
R/(W) *
5
0
IRQ4F
R/(W) *
4
0
IRQ to IRQ flags
These bits indicate IRQ to IRQ
interrupt request status
IRQ3F
R/(W) *
Rev.5.00 Sep. 12, 2007 Page 89 of 764
3
0
5
IRQ2F
R/(W) *
0
2
0
0
to IRQ
5. Interrupt Controller
IRQ1F
R/(W) *
5
1
0
REJ09B0396-0500
5
interrupt
(Initial value)
(Initial value)
IRQ0F
R/(W) *
0
0
0