HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 198

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
Example of Program Setup Procedure: Figure 6.32 shows an example of the program setup
procedure.
6.5.13
Note the following points when using the DRAM refresh function.
• Refresh cycles will not be executed when the external bus released state, software standby
• If a refresh request is generated internally while the external bus is released, the first request is
• When a bus cycle is extended by means of wait state insertion, the first request is retained in
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mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore be
performed by other means in these cases.
retained and a single refresh cycle will be executed after the bus-released state is cleared.
Figure 6.33 shows the bus cycle in this case.
the same way as when the external bus has been released.
In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.34).
When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before
executing the SLEEP instruction.
Usage Notes
Figure 6.32 Example of Setup Procedure when Using DRAM Interface
Set bits CKS2 to CKS0 in RTMCSR
Wait for DRAM stabilization time
DRAM can be accessed
Set ABWCR
Set RTCOR
Set DRCRB
Set DRCRA