HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 149

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 0⎯Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
6.2.5
Bit
Initial value
Read/Write
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7⎯Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
0
1
Bit 6⎯Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
0
1
Bus Control Register (BCR)
ICIS1
R/W
Description
The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
The bus can be released to an external device
Description
No idle cycle inserted in case of consecutive external read cycles for different
areas
Idle cycle inserted in case of consecutive external read cycles for different
areas
Description
No idle cycle inserted in case of consecutive external read and write cycles
Idle cycle inserted in case of consecutive external read and write cycles
7
1
ICIS0
R/W
6
1
BROME BRSTS1 BRSTS0
R/W
5
0
R/W
4
0
Rev.5.00 Sep. 12, 2007 Page 119 of 764
R/W
3
0
⎯
⎯
2
1
REJ09B0396-0500
RDEA
6. Bus Controller
R/W
1
1
(Initial value)
(Initial value)
(Initial value)
WAITE
R/W
0
0