HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 272

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7. DMA Controller
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before
the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the
next interrupt does not occur before the DMA transfers end on all the activated channels. If the
next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was
selected may fail to accept further activation requests.
7.6.6
If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.
• When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then
• If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The
• While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does
• When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted
7.6.7
Table 7.14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Table 7.14 Address Ranges Specifiable in MAR and IOAR
MAR
IOAR
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REJ09B0396-0500
clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.
It is possible to find whether a transfer was halted in the middle of a block by checking the
block size counter. If the block size counter does not have its initial value, the transfer was
halted in the middle of a block.
activation request is not held pending.
not accept activating interrupt requests. If an activating interrupt occurs in this state, the
DMAC does not operate and does not hold the transfer request pending internally. Neither is a
CPU interrupt requested.
For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating
interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See
section 7.6.5, Note on Activating DMAC by Internal Interrupts.
in the middle of a block transfer, the rest of the block is transferred when the next transfer
request occurs. Otherwise, the next block is transferred when the next transfer request occurs.
Memory and I/O Address Register Values
NMI Interrupts and Block Transfer Mode
1-Mbyte Mode
H'00000 to H'FFFFF
(0 to 1048575)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)