HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 129

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
UE = 0: The I and UI bits in the CPU's CCR and the IPR bits enable three-level masking of
IRQ
• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and
• For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
interrupt request is sent to the interrupt controller.
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
current instruction has been completed.
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
starts executing from the address indicated by the contents of the vector address.
when the I bit is cleared to 0.
are unmasked when either the I bit or the UI bit is cleared to 0.
H'20, and IPRB is set to H'00 (giving IRQ
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ
b. If I = 1 and UI = 0, only NMI, IRQ
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
0
to IRQ
5
interrupts and interrupts from the on-chip supporting modules.
2
, and IRQ
2
and IRQ
3
are unmasked.
3
interrupt requests priority over other
Rev.5.00 Sep. 12, 2007 Page 99 of 764
2
> IRQ
5. Interrupt Controller
3
>IRQ
REJ09B0396-0500
0
…).