HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 292

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
8. I/O Ports
8.6.2
Table 8.9 summarizes the registers of port 9.
Table 8.9
Address*
H'EE008
H'FFFD8
Note:
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select
input or output for each pin in port 9.
Bits 7 and 6 are reserved. They cannot be modified and always read as 1.
Bit
Initial value
Read/Write
When a pin in port 9 becomes an output port if the corresponding P9DDR bit is set to 1, and an
input port if this bit is cleared to 0.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. When transition is made to software standby mode while a P9DDR
bit is set to 1, the corresponding pin maintains its output state.
Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data
for port 9. When port 9 functions as an output port, the value of this register is output. When a bit
in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a
bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
Rev.5.00 Sep. 12, 2007 Page 262 of 764
REJ09B0396-0500
* Lower 20 bits of the address in advanced mode.
Register Configuration
Port 9 Registers
Name
Port 9 data direction register
Port 9 data register
Reserved bits
7
1
6
1
P9 DDR
5
W
5
0
P9 DDR
4
W
4
0
Abbreviation
P9DDR
P9DR
Port 9 data direction 5 to 0
These bits select input or
output for port 9 pins
P9 DDR
3
W
3
0
P9 DDR
R/W
W
R/W
2
W
2
0
P9 DDR
H'C0
H'C0
1
Initial Value
W
1
0
P9 DDR
0
W
0
0

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