HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 333

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

9.2.6
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
Initial value
Read/Write
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 6⎯Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 flag when OVF2 is set to 1.
Bit 6
OVIE2
0
1
Bit 5⎯Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 flag when OVF1 is set to 1.
Bit 5
OVIE1
0
1
Note:
*
Bit
Timer Interrupt Status Register C (TISRC)
Only 0 can be written, to clear the flag.
Description
OVI2 interrupt requested by OVF2 flag is disabled
OVI2 interrupt requested by OVF2 flag is enabled
Description
OVI1 interrupt requested by OVF1 flag is disabled
OVI1 interrupt requested by OVF1 flag is enabled
Reserved bit
⎯
⎯
7
1
OVIE2
R/W
6
0
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
OVIE1
R/W
5
0
OVIE0
R/W
4
0
Reserved bit
⎯
⎯
3
1
Rev.5.00 Sep. 12, 2007 Page 303 of 764
R/(W)*
OVF2
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
2
0
R/(W)*
OVF1
1
0
R/(W)*
OVF0
REJ09B0396-0500
0
0
9. 16-Bit Timer
(Initial value)
(Initial value)