HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 327

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 0⎯PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
0
1
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
9.2.4
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables general register compare match and input capture interrupt requests.
Initial value
Read/Write
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
Note:
Bit
Timer Interrupt Status Register A (TISRA)
*
Description
Channel 0 operates normally
Channel 0 operates in PWM mode
Only 0 can be written, to clear the flag.
Reserved bit
⎯
⎯
7
1
IMIEA2
R/W
6
0
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
IMIEA1
R/W
5
0
IMIEA0
R/W
4
0
Reserved bit
⎯
⎯
3
1
Rev.5.00 Sep. 12, 2007 Page 297 of 764
R/(W)*
IMFA2
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
0
2
0
becomes a PWM output pin. The
R/(W)*
IMFA1
1
0
R/(W)*
IMFA0
REJ09B0396-0500
0
0
9. 16-Bit Timer
(Initial value)