HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 690

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix B Internal I/O Registers
DRCRB⎯DRAM Control Register B
Rev.5.00 Sep. 12, 2007 Page 660 of 764
REJ09B0396-0500
Initial value
Read/Write
Multiplex control 1 and 0
Bit
MXC1
0
1
MXC1
R/W
7
0
MXC0
CAS output pin select
0
1
0
1
0
1
MXC0
R/W
Refresh cycle enable
PB4 and PB5 selected as UCAS and LCAS output pins
HWR and LWR selected as UCAS and LCAS output pins
6
0
Column address: 8 bits
Compared address:
Column address: 9 bits
Compared address:
Column address: 10 bits
Compared address:
Illegal setting
0
1
Modes 1, 2
Modes 3, 4
Modes 1, 2
Modes 3, 4
Modes 1, 2
Modes 3, 4
TP cycle control
0
1
Refresh cycles are disabled
DRAM refresh cycles are enabled
CSEL
R/W
5
0
1-state precharge cycle is inserted
2-state precharge cycle is inserted
RAS-CAS wait
0
1
Refresh cycle wait control
RCYCE
0
1
Wait state (T
1 wait state (T
R/W
4
0
Wait state (T
1 wait state (T
H'EE027
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
⎯
⎯
Description
3
1
rW
rW
) insertion is disabled
RW
) is inserted
RW
TPC
R/W
) insertion is disabled
2
0
) is inserted
RCW
R/W
1
0
A
A
A
A
A
A
A
A
A
A
A
A
19
19
23
23
19
19
23
23
19
19
23
23
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
RLW
R/W
0
0
8
9
8
9
9
10
9
10
10
11
10
11
DRAM interface