HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

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To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
Old Company Name in Catalogs and Other Documents
http://www.renesas.com
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for HD6413007F20

HD6413007F20 Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3006, H8/3007 16 Hardware Manual Renesas 16-Bit ...

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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

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Rev.5.00 Sep. 12, 2007 Page iv of xxviii REJ09B0396-0500 ...

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The H8/3006 and H8/3007 are a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set ...

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Rev.5.00 Sep. 12, 2007 Page vi of xxviii REJ09B0396-0500 ...

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Main Revisions for This Edition Item Page ⎯ All 5.4.2 Interrupt 102 Sequence Figure 5.7 Interrupt Sequence 8.7.2 Register 274 Configuration Table 8.14 Port A Pin Functions (Modes /TP /TIOCB /TCLKD /TP ...

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Item Page 8.7.2 Register 276 Configuration Table 8.14 Port A Pin Functions (Modes /TP /TCLKB/TEND /TP /TCLKA/TEND 277 Rev.5.00 Sep. 12, 2007 Page viii of xxviii REJ09B0396-0500 Revision (See ...

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Item Page 8.8.2 Register 281 Configuration Port B Data Register (PBDR): Table 8.16 Port B Pin Functions PB /TP /TMIO /DREQ / /TP /TMO /CS 282 /TP /TMIO ...

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Item Page 9.4.6 Setting Initial 333 Value of 16-Bit Timer Output Figure 9.32 Example of Timing for Setting Initial Value of 16-Bit Timer Output by Writing to TOLR 10.2.3 Time Constant 357 Registers B (TCORB) 10.2.4 Timer Control 359 Register ...

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Item Page 10.4.5 Operation with 373 Cascaded Connection 375 10.4.6 Input Capture 376 Setting 11.3.3 Normal TPC 406 Output Figure 11.4 Setup Procedure for Normal TPC Output (Example) Figure 11.5 Normal 407 TPC Output Example (Five-Phase Pulse Output) 13.1 Overview ...

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Item Page 14.3.4 Register 499 Settings Smart Card Mode Register (SCMR) Settings: 14.4 Usage Notes 511 Note on Block Transfer Mode Support: 15.1 Overview 513 15.2.1 A/D Data 517 Registers (ADDRA to ADDRD) 16.1.3 Pin 536 Configuration ...

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Item Page C.3 Port 7 Block 724 Diagrams Figure C.3 (b) Port 7 Block Diagram (Pins P7 6 and C.7 Port B Block 742 Diagrams Figure C.7 (e) Port B Block Diagram (Pin Figure ...

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Item Page Appendix H 759 Comparison of H8/300H Series Product Specifications H.1 Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3002 All trademarks and registered trademarks are the property of their respective owners. Rev.5.00 Sep. 12, ...

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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1.3.3 Pin Assignments in Each Mode ........................................................................... 14 Section 2 CPU ...................................................................................................................... 19 2.1 Overview........................................................................................................................... 19 2.1.1 Features................................................................................................................ 19 ...

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Reset State ........................................................................................................... 54 2.8.7 Power-Down State ............................................................................................... 54 2.9 Basic Operational Timing ................................................................................................. 55 2.9.1 Overview.............................................................................................................. 55 2.9.2 On-Chip Memory Access Timing........................................................................ 55 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 56 2.9.4 Access to External Address Space ....................................................................... ...

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Block Diagram ..................................................................................................... 80 5.1.3 Pin Configuration................................................................................................. 81 5.1.4 Register Configuration......................................................................................... 81 5.2 Register Descriptions ........................................................................................................ 82 5.2.1 System Control Register (SYSCR) ...................................................................... 82 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 83 5.2.3 IRQ Status Register ...

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Operation .......................................................................................................................... 130 6.3.1 Area Division....................................................................................................... 130 6.3.2 Bus Specifications................................................................................................ 132 6.3.3 Memory Interfaces............................................................................................... 133 6.3.4 Chip Select Signals .............................................................................................. 133 6.4 Basic Bus Interface ........................................................................................................... 134 6.4.1 Overview.............................................................................................................. 134 6.4.2 Data Size and Data Alignment............................................................................. 134 6.4.3 Valid ...

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BREQ Pin Input Timing ...................................................................................... 186 Section 7 DMA Controller 7.1 Overview........................................................................................................................... 187 7.1.1 Features................................................................................................................ 187 7.1.2 Block Diagram ..................................................................................................... 188 7.1.3 Functional Overview............................................................................................ 188 7.1.4 Pin Configuration................................................................................................. 190 7.1.5 Register Configuration......................................................................................... 190 7.2 Register Descriptions (1) (Short Address ...

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Note on Activating DMAC by Internal Interrupts ............................................... 241 7.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 242 7.6.7 Memory and I/O Address Register Values .......................................................... 242 7.6.8 Bus Cycle when Transfer Is Aborted ................................................................... 243 7.6.9 Transfer Requests ...

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Timer Interrupt Status Register A (TISRA)......................................................... 297 9.2.5 Timer Interrupt Status Register B (TISRB) ......................................................... 300 9.2.6 Timer Interrupt Status Register C (TISRC) ......................................................... 303 9.2.7 Timer Counters (16TCNT) .................................................................................. 305 9.2.8 General Registers (GRA, GRB)........................................................................... 306 9.2.9 Timer ...

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Compare Match Timing....................................................................................... 369 10.4.3 Input Capture Signal Timing ............................................................................... 371 10.4.4 Timing of Status Flag Setting .............................................................................. 372 10.4.5 Operation with Cascaded Connection.................................................................. 373 10.4.6 Input Capture Setting ........................................................................................... 375 10.5 Interrupt ............................................................................................................................ 376 10.5.1 Interrupt Source ................................................................................................... ...

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Overview.............................................................................................................. 404 11.3.2 Output Timing...................................................................................................... 405 11.3.3 Normal TPC Output............................................................................................. 406 11.3.4 Non-Overlapping TPC Output ............................................................................. 408 11.3.5 TPC Output Triggering by Input Capture ............................................................ 410 11.4 Usage Notes ...................................................................................................................... 410 11.4.1 Operation of TPC Output Pins ............................................................................. 410 ...

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Serial Control Register (SCR).............................................................................. 436 13.2.7 Serial Status Register (SSR) ................................................................................ 441 13.2.8 Bit Rate Register (BRR) ...................................................................................... 446 13.3 Operation .......................................................................................................................... 454 13.3.1 Overview.............................................................................................................. 454 13.3.2 Operation in Asynchronous Mode ....................................................................... 457 13.3.3 Multiprocessor Communication........................................................................... 466 13.3.4 Synchronous ...

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A/D Control/Status Register (ADCSR) ............................................................... 518 15.2.3 A/D Control Register (ADCR) ............................................................................ 520 15.3 CPU Interface.................................................................................................................... 522 15.4 Operation........................................................................................................................... 523 15.4.1 Single Mode (SCAN = 0)..................................................................................... 523 15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 525 15.4.3 Input Sampling and ...

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Register Configuration......................................................................................... 553 18.5.2 Division Control Register (DIVCR) .................................................................... 553 18.5.3 Usage Notes ......................................................................................................... 554 Section 19 Power-Down State 19.1 Overview........................................................................................................................... 555 19.2 Register Configuration...................................................................................................... 557 19.2.1 System Control Register (SYSCR) ...................................................................... 557 19.2.2 Module Standby Control Register H ...

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DRAM Interface Bus Timing .............................................................................. 599 20.3.5 TPC and I/O Port Timing..................................................................................... 602 20.3.6 Timer Input/Output Timing ................................................................................. 603 20.3.7 SCI Input/Output Timing ..................................................................................... 604 20.3.8 DMAC Timing..................................................................................................... 605 Appendix A Instruction Set A.1 Instruction List .................................................................................................................. 607 A.2 ...

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Rev.5.00 Sep. 12, 2007 Page xxviii of xxviii REJ09B0396-0500 ...

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Overview The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general ...

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Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers eight 32-bit registers) High-speed ...

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Feature Description • Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area • Chip select output available for areas • 8-bit access or 16-bit access selectable for each area ...

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Overview Feature Description • 8-bit timer, 8-bit up-counter (external event count capability) 4 channels • Two time constant registers • Two channels can be connected • Programmable Maximum 16-bit pulse output, using 16-bit timer as time base timing pattern ...

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Feature Description Operating Four MCU operating modes modes Mode Address Space Address Pins Initial Bus Width Max. Bus Width Mode 1 1 Mbyte Mode 2 1 Mbyte Mode 3 16 Mbytes Mode 4 16 Mbytes • Power-down Sleep mode state ...

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Overview 1.2 Internal Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES RESO NMI AS RD HWR LWR φ/P6 7 BACK/P6 2 BREQ/P6 1 WAIT/ /P8 0 ...

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Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3006, H8/3007 FP-100B and TFP-100B packages is shown in figure 1.2, and that of the FP-100A package in figure 1. REF P7 /AN 78 ...

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Overview /AN / /AN / ...

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Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Power 11, 22, SS 44, 57, 65, 92 Clock XTAL 67 EXTAL 66 ...

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Overview Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O RES System 63 control RESO 10 STBY 62 BREQ 59 BACK 60 Interrupts NMI 64 IRQ to 17, 16, 5 IRQ Address 100 ...

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FP-100B Type Symbol TFP-100B FP-100A I/O RFSH DRAM 87 interface CS to 89, 88 HWR 71 UCAS 6 LWR 72 LCAS 7 DREQ DMA , DREQ controller 0 (DMAC) TEND ...

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Overview Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Program mable TP 100 timing pattern controller (TPC) Serial TxD communi- TxD 0 cation RxD to ...

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Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O I/O ports 23 ...

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Overview 1.3.3 Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. FP-100B TFP-100B FP-100A Mode ...

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Pin No. FP-100B TFP-100B FP-100A Mode ...

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Overview Pin No. FP-100B TFP-100B FP-100A Mode STBY 62 64 RES ...

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Pin No. FP-100B TFP-100B FP-100A Mode ADTRG TEND TEND 95 97 ...

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Overview Rev.5.00 Sep. 12, 2007 Page 18 of 764 REJ09B0396-0500 ...

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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...

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CPU • High-speed operation ⎯ All frequently-used instructions execute in two to four states ⎯ Maximum clock frequency: ⎯ 8/16/32-bit register-register add/subtract: 100 ns ⎯ 8 × 8-bit register-register multiply: ⎯ 16 ÷ 8-bit register-register divide: ⎯ 16 × ...

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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. CPU operating modes Note: * Normal mode is not available in ...

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CPU 2.3 Address Space Figure 2.2 shows a simple memory map for the H8/3006 and H8/3007. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in ...

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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...

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CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a ...

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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...

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CPU Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign ...

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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...

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CPU General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend :: ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least ...

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Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Address 7 Address Address ...

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CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 64 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction Data transfer MOV, PUSH* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, ...

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Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction #xx Rn Data MOV BWL BWL transfer ⎯ ⎯ POP, PUSH ⎯ ⎯ MOVFPE, MOVTPE Arithmetic ADD, ...

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CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* ...

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Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd ...

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CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers immediate data and data in a ...

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Instruction Size* Function Rd ÷ Rs → Rd DIVXU B/W Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient ...

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CPU Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ ...

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Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower ...

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CPU Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C BOR B ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number ...

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Table 2.8 Branching Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC ...

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CPU Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling ⎯ RTE Returns from an exception-handling routine ⎯ SLEEP Causes a transition to the power-down state (EAs) → CCR LDC B/W Moves the source ...

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Table 2.10 Block Transfer Instruction Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B repeat until else next; EEPMOV.W ⎯ ≠ 0 then repeat until else next; Block transfer instruction. This instruction transfers the number of data ...

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CPU Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, ...

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Before Execution of BCLR Instruction Input/output Input Input DDR 0 0 Execution of BCLR Instruction BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output DDR 1 1 Explanation: To execute ...

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CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the ...

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Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @–ERn: • Register indirect with post-increment⎯@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After ...

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CPU 7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit ...

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Table 2.13 Effective Address Calculation Rev.5.00 Sep. 12, 2007 Page 47 of 764 REJ09B0396-0500 2. CPU ...

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CPU Rev.5.00 Sep. 12, 2007 Page 48 of 764 REJ09B0396-0500 ...

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Rev.5.00 Sep. 12, 2007 Page 49 of 764 REJ09B0396-0500 2. CPU ...

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CPU 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. ...

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Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, ...

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CPU Reset Exception Interrupt sources Trap instruction Figure 2.12 Classification of Exception Sources End of bus release Bus-released state End of exception handling Exception-handling state RES = High *1 Reset state Notes: 1. From any state except hardware standby ...

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Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception ...

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CPU 2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, ...

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Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or bus ...

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CPU φ Address bus AS RD HWR LWR , , , Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. ...

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Address bus AS RD HWR LWR , , , Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas ...

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CPU Rev.5.00 Sep. 12, 2007 Page 58 of 764 REJ09B0396-0500 ...

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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3006 and H8/3007 have four operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The ...

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MCU Operating Modes When changing the mode, the chip must be placed in the reset state before the mode pin inputs are changed. 3.1.2 Register Configuration The H8/3006 and H8/3007 have a mode control register (MDCR) that indicates the ...

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System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3006 and H8/3007. Bit 7 6 SSBY STS2 Initial value 0 0 Read/Write R/W R/W Standby timer select These bits select ...

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MCU Operating Modes Bits 6 to 4⎯Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby ...

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Bit 1⎯Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS bus control signals (CS 0 outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description 0 In ...

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MCU Operating Modes 3.4.3 Mode 3 Part of port A function as address pins A address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas least one area is ...

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Memory Map in Each Operating Mode Figures 3.1 and 3.2 show a memory maps of the H8/3006 and H8/3007. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also ...

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MCU Operating Modes Modes 1 and 2 (1 Mbyte) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Internal I/O registers (1) H'EE0FF External address H'F8000 ...

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Modes 1 and 2 (1 Mbyte) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area 5 H'BFFFF H'C0000 Area 6 ...

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MCU Operating Modes Rev.5.00 Sep. 12, 2007 Page 68 of 764 REJ09B0396-0500 ...

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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...

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Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • Interrupts ...

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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...

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Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the ...

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Figure 4.2 Reset Sequence (Modes 1 and 3) 4. Exception Handling Rev.5.00 Sep. 12, 2007 Page 73 of 764 REJ09B0396-0500 ...

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Exception Handling φ RES Address bus RD HWR LWR , High (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) ...

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Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting ...

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Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit to ...

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Notes on Stack Usage When accessing word data or longword data, the H8/3006 and H8/3007 regard the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the ...

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Exception Handling Rev.5.00 Sep. 12, 2007 Page 78 of 764 REJ09B0396-0500 ...

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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in ...

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Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . TEI TEIE Interrupt controller Legend: ISCR: IRQ ...

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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers 1 ...

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Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the ...

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Bit 2⎯NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG Description 0 Interrupt is requested at falling edge of NMI input 1 Interrupt is requested at rising edge of NMI input 5.2.2 Interrupt Priority Registers A and ...

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Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level of ...

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Bit 7⎯Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6⎯Priority Level ...

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Interrupt Controller Bit 2⎯Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 1 16-bit ...

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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level of 8-bit timer channel ...

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Interrupt Controller Bit 7⎯Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 0 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 1 ...

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Bit 2⎯Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description 0 SCI channel 1 interrupt requests have priority level 0 (low priority) 1 SCI channel 1 interrupt requests have priority level ...

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Interrupt Controller Bits 5 to 0⎯IRQ to IRQ Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ 5 0 IRQ interrupt requests. 0 Bits IRQ5F to IRQ0F Description 0 [Clearing conditions] • ...

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IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 5 0 Bit 7 ⎯ ⎯ Initial value 0 Read/Write R/W R/W ...

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Interrupt Controller 5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ IRQ can be used to exit software standby mode. 2 NMI: NMI is the highest-priority ...

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Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to ...

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Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 ⎯ Reserved WOVI Watchdog (interval timer) timer CMI DRAM (compare match) ...

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Interrupt Source Origin IMIA2 16-bit timer (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) ⎯ Reserved CMIA0 8-bit timer (compare match channel 0/1 A0) CMIB0 (compare match B0) CMIA1/CMIB1 (compare match A1/B1) ...

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Interrupt Controller Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 RXI1 (receive data full 1) TXI1 ...

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Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3006 and H8/3007 handle interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are controlled ...

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Interrupt Controller Priority level 1? No IRQ 0 Yes IRQ Figure 5.4 Process Up to Interrupt Acceptance when Rev.5.00 Sep. 12, 2007 Page 98 of 764 REJ09B0396-0500 Program execution state Interrupt requested? Yes Yes NMI No ...

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If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- ...

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Interrupt Controller Figure 5.5 shows the transitions among the above states. a. All interrupts are unmasked ← Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when UE = ...

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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes TEI2 Yes Yes Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.6 Process ...

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Interrupt Controller 5.4.2 Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Rev.5.00 Sep. 12, 2007 Page ...

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Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item 1 Interrupt priority decision ...

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Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. ...

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Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting ...

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Interrupt Controller Rev.5.00 Sep. 12, 2007 Page 106 of 764 REJ09B0396-0500 ...

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Section 6 Bus Controller 6.1 Overview The H8/3006 and H8/3007 have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be ...

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Bus Controller • Burst ROM interface ⎯ Burst ROM interface can be set for area 0 ⎯ Selection of two- or three-state burst access • Idle cycle insertion ⎯ An idle cycle can be inserted in case of an ...

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Area Internal address bus decoder WAIT Internal signals CPU bus request signal DMAC bus request signal DRAM interface bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal DRAM interface bus acknowledge signal DRAM control Legend: ABWCR : Bus ...

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Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write ...

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Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers 1 Address* Name H'EE020 Bus width control register H'EE021 Access state control register H'EE022 Wait control register H H'EE023 Wait control register L H'EE013 Bus ...

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Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit 7 ABW7 Initial value 1 Modes 1 and 3 Read/Write R/W Modes ...

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Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. Bit 7 AST7 AST6 Initial value 1 Read/Write R/W ASTCR is initialized to H'FF by ...

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Bus Controller WCRH Bit 7 W71 Initial value 1 Read/Write R/W Bits 7 and 6⎯Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is ...

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Bits 3 and 2⎯Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit ...

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Bus Controller Bits 7 and 6⎯Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set ...

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Bits 1 and 0⎯Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit ...

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Bus Controller Bit 7⎯Address 23 Enable (A23E): Enables this bit enables A output from PA 23 has its ordinary port functions. Bit 7 A23E Description the input/output ...

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Bit 0⎯Bus Release Enable (BRLE): Enables or disables release of the bus to an external device. Bit 0 BRLE Description 0 The bus cannot be released to an external device BREQ and BACK can be used as input/output pins 1 ...

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Bus Controller Bit 5⎯Burst ROM Enable (BROME): Selects whether area burst ROM interface area. Bit 5 BROME Description 0 Area basic bus interface area 1 Area burst ROM interface area ...

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Bit 0⎯WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE Description WAIT pin wait input is disabled, and the WAIT pin can be used input/output port WAIT pin ...

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Bus Controller 6.2.7 DRAM Control Register A (DRCRA) Bit 7 DRAS2 DRAS1 Initial value 0 Read/Write R/W DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables ...

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When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4⎯Reserved: This bit cannot be modified and is always read as 1. Bit 3⎯Burst Access ...

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Bus Controller Bit 0⎯Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas are not designated as DRAM space, this bit should not be set to 1. Bit 0 RFSHE Description RFSH ...

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Bits 7 and 6⎯Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface. In burst operation, the row address used for comparison is determined by the setting of these ...

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Bus Controller Bit 4⎯Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle insertion. When none of areas has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. ...

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Refresh Timer Control/Status Register (RTMCSR) Bit 7 CMF CMIE Initial value 0 Read/Write R/(W)* RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also ...

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Bus Controller Bits 5 to 3⎯Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 clocks obtained by dividing the system clock (φ). When the input clock is selected ...

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Refresh Time Constant Register (RTCOR) Bit 7 Initial value 1 Read/Write R/W RTCOR is an 8-bit readable/writable register that sets the RTCNT compare-match interval. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set ...

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Bus Controller 6.3 Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 ...

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H'000000 2 Mbytes H'1FFFFF H'200000 2 Mbytes H'3FFFFF H'400000 2 Mbytes H'5FFFFF H'600000 2 Mbytes H'7FFFFF H'800000 2 Mbytes H'9FFFFF H'A00000 2 Mbytes H'BFFFFF H'C00000 2 Mbytes H'DFFFFF H'E00000 1.93 Mbytes H'FEE000 Internal I/O registers (1) H'FEE0FF H'FEE100 H'FF7FFF H'FF8000 ...

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Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip ...

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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL ABWn ASTn Wn1 ⎯ ⎯ 6.3.3 Memory Interfaces The H8/3006 and H8/3007 memory interfaces comprise a basic ...

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Bus Controller Output Output register (CSCR). A reset leaves pins the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports. ...

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Access Areas: Figure 6.5 illustrates data alignment control for 8-bit access space. With 8-bit access space, the upper data bus (D can be accessed at one time is one byte: a word access is performed as two byte accesses, ...

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Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used, and the valid strobes, for the access spaces read, the RD signal is valid for both the upper and the lower half of the data ...

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The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4. Areas When area external space is accessed, signals CS Basic bus ...

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Bus Controller 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.7 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D pin is always high. Wait states can be inserted. ...

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Two-State-Access Areas: Figure 6.8 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper data bus (D pin is always high. Wait states cannot be inserted. Address bus Read access Write access Note ...

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Bus Controller 16-Bit, Three-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D even addresses and the lower data bus (D inserted. φ ...

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Address bus Read access HWR LWR Write access Note Figure ...

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Bus Controller φ Address bus Read access HWR LWR Write access Note Figure 6.11 ...

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Two-State-Access Areas: Figures 6.12 to 6.14 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D even addresses and the lower data bus (D be inserted. Address bus Read ...

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Bus Controller Address bus Read access Write access Note Figure 6.13 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) Rev.5.00 Sep. 12, 2007 Page 144 of 764 REJ09B0396-0500 Bus cycle T 1 φ ...

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Address bus Read access Write access Note Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) 6.4.6 Wait Control When accessing external space, the H8/3006 and H8/3007 can extend the bus cycle by ...

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Bus Controller Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT ...

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DRAM Interface 6.5.1 Overview The H8/3006 and H8/3007 are provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external ...

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Bus Controller 6.5.3 Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the ...

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Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins With DRAM Pin Designated Name UCAS PB4 Upper column address strobe LCAS PB5 Lower column address strobe ...

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Bus Controller If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is ...

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Precharge State Control In the H8/3006 and H8/3007, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (T two T states by setting the TPC bit DRCRB. The optimum ...

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Bus Controller 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the T between the T state and T state Insertion of T Wait State between setting the ...

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Byte Access Control and CAS Output Pin 6.5.9 When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external data ...

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Bus Controller φ CSn (RAS) PB4(UCAS) Byte control PB5(LCAS) RD(WE) Note Figure 6.19 Control Timing (Upper-Byte Write Access When CSEL = 0) 6.5.10 Burst Operation With DRAM, in addition ...

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CSn(RAS) PB4 /PB5 (UCAS /LCAS) Read access RD(WE PB4 /PB5 (UCAS/LCAS) Write access RD(WE Note Figure 6.20 Operation ...

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Bus Controller Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB Operating Mode MXC1 Modes 1 and 2 0 (1-Mbyte) 1 Modes 3 and 4 0 (16-Mbyte) 1 ...

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DRAM access φ CSn (RAS) PB4/PB5 (UCAS/LCAS Note Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0) ...

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Bus Controller φ RASn φ RASn φ RASn φ RASn Note Figure 6.22 RASn Negation Timing when RAS Down Mode Is Selected Rev.5.00 Sep. 12, 2007 Page 158 of 764 REJ09B0396-0500 DRAM access cycle ...

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When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval ...

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Bus Controller 6.5.11 Refresh Control The H8/3006 and H8/3007 are provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit DRCRB. ...

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RTCNT RTCOR Refresh request signal and CMF bit setting signal φ Address bus CS (RAS) n PB4/PB5 (UCAS/LCAS) RD(WE) RFSH AS Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0) The basic CBS refresh ...

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Bus Controller Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (T be inserted between the T state and T R1 The RLW bit setting is valid only for CBR refresh ...

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Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. The H8/3006 and H8/3007 have a function that places the ...

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Bus Controller Refresh Signal (RFSH): A refresh signal (RFSH) that transmits a refresh cycle off-chip can be output by setting the RFSHE bit DRCRA. RFSH output timing is shown in figures 6.26, 6.27, and 6.28. 6.5.12 ...

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Connection Examples • Figure 6.29 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs using a × 16-bit organization, and the corresponding address map. The DRAMs used in this example are of the 10-bit row address × 10-bit column ...

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Bus Controller • Figure 6.30 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit organization, and the corresponding address map. The DRAMs used in this example are of the 11-bit row address × 10-bit column address ...

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Figure 6.31 shows typical interconnections when using two 4-Mbit DRAMs, and the corresponding address map. The DRAMs used in this example are of the 9-bit row address × 9-bit column address type. In this example, upper address decoding allows ...

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Bus Controller Example of Program Setup Procedure: Figure 6.32 shows an example of the program setup procedure. Figure 6.32 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes Note the following points when using the DRAM refresh ...

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Similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. This can also be avoided by clearing the BRLW bit BRCR. • Immediately after self-refreshing is cleared, external bus release is possible during ...

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Bus Controller Oscillation stabilization time on exit from software standby mode φ Address bus RAS CAS 6.6 Interval Timer 6.6.1 Operation When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as ...

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