HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 200

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
6. Bus Controller
6.6
6.6.1
When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as
an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR,
selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag
in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match.
The compare match signal is generated in the last state in which the values match (when RTCNT
is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR
match, the compare match signal is not generated until the next counter clock pulse. Figure 6.36
shows the timing.
Rev.5.00 Sep. 12, 2007 Page 170 of 764
REJ09B0396-0500
Interval Timer
Operation
Address bus
RAS
CAS
φ
Oscillation stabilization
time on exit from software
standby mode
Figure 6.35 Self-Refresh Clearing
CPU internal cycle
bus can be released)
(period in which external
CPU cycle
@SP

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