HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 395

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
TCORB0 and TCORB2 function as compare match registers regardless of the setting of bit 4 of
8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1
(8TCSR3)
0
1
• When the compare match register function is used, the timer output priority order is: toggle
• If compare match A and B occur simultaneously, the output changes in accordance with the
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0⎯Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
• When the compare match register function is used, the timer output priority order is: toggle
• If compare match A and B occur simultaneously, the output changes in accordance with the
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
output > 1 output > 0 output.
higher-priority compare match.
output > 1 output > 0 output.
higher-priority compare match.
Bit 0
OS0
0
1
0
1
Bit 3
OIS3
0
1
0
1
Description
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
Bit 2
OIS2
0
1
0
1
0
1
0
1
Description
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
Rev.5.00 Sep. 12, 2007 Page 365 of 764
REJ09B0396-0500
10. 8-Bit Timers
(Initial value)
(Initial value)