HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 448

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12. Watchdog Timer
12.2.3
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
Initial value
Read/Write
Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7⎯Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3006 and
H8/3007 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO
pin to initialize external system devices.
Rev.5.00 Sep. 12, 2007 Page 418 of 764
REJ09B0396-0500
Bit 7
WRST
0
1
Register Access.
* Only 0 can be written in bit 7, to clear the flag.
[Clearing condition]
Reset signal at RES pin.
Read WRST when WRST =1, then write 0 in WRST.
Reset Control/Status Register (RSTCSR)
Description
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W)
WRST
7
0
*
Reset output enable
Enables or disables external output of the reset signal
RSTOE
R/W
6
0
⎯
⎯
5
1
⎯
⎯
4
1
Reserved bits
⎯
⎯
3
1
⎯
⎯
2
1
⎯
⎯
1
1
(Initial value)
⎯
⎯
0
1