HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 711

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

TISRA⎯Timer Interrupt Status Register A
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Bit
⎯
⎯
7
1
IMIEA2
R/W
Input capture/compare match interrupt enable A2
6
0
0
1
IMIA2 interrupt requested by IMFA2 flag is disabled
IMIA2 interrupt requested by IMFA2 flag is enabled
IMIEA1
R/W
Input capture/compare match interrupt enable A1
5
0
0
1
IMIA1 interrupt requested by IMFA1 flag is disabled
IMIA1 interrupt requested by IMFA1 flag is enabled
IMIEA0
R/W
Input capture/compare match interrupt enable A0
4
0
0
1
Input capture/compare match flag A2
IMIA0 interrupt requested by IMFA0 flag is disabled
IMIA0 interrupt requested by IMFA0 flag is enabled
0
1
⎯
⎯
3
1
Input capture/compare match flag A1
[Clearing conditions]
• Read IMFA2 when IMFA2 =1, then write 0 in IMFA2
• DMAC activated by IMIA2 interrupt
[Setting conditions]
• 16TCNT2 = GRA2 when GRA2 functions as an output
• 16TCNT2 value is transferred to GRA2 by an input capture
0
1
compare register
signal when GRA2 functions as an input capture register
Input capture/compare match flag A0
R/(W)*
IMFA2
0
1
[Clearing conditions]
• Read IMFA1 when IMFA1 =1, then write 0 in IMFA1
• DMAC activated by IMIA1 interrupt
[Setting conditions]
• 16TCNT1 = GRA1 when GRA1 functions as an output
• 16TCNT1 value is transferred to GRA1 by an input capture
2
0
H'FFF64
compare register
signal when GRA1 functions as an input capture register
[Clearing conditions]
• Read IMFA0 when IMFA0 =1, then write 0 in IMFA0
• DMAC activated by IMIA0 interrupt
[Setting conditions]
• 16TCNT0 = GRA0 when GRA0 functions as an output
• 16TCNT0 value is transferred to GRA0 by an input
compare register.
capture signal when GRA0 functions as an input
capture register.
R/(W)*
Rev.5.00 Sep. 12, 2007 Page 681 of 764
IMFA1
1
0
Appendix B Internal I/O Registers
R/(W)*
IMFA0
0
0
(Initial value)
16-Bit Timer (Common)
(Initial value)
REJ09B0396-0500
(Initial value)
(Initial value)
(Initial value)
(Initial value)