HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 307

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Pin
PA
TCLKA/
TEND
8.8
8.8.1
Port B is an 8-bit input/output port that is also used for output (TP
programmable timing pattern controller (TPC), input/output (TMIO
the 8-bit timer, CS
and output (TxD
(UCAS, LCAS) by the DRAM interface. See table 8.16 for the selection of pin functions.
A reset or hardware standby transition leaves port B as an input port. For output of CS
modes 1 to 4, see section 6.3.4, Chip Select Signals. Pins not assigned to any of these functions are
available for generic input/output. When DRAM is connected to areas 2 to 5, the CS
output pins function as RAS output pins for each area. For details see section 6.5, DRAM
Interface. Figure 8.7 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington
transistor pair.
0
/TP
0
0
/
Port B
Overview
Pin Functions and Selection Method
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit
PA
PA
NDER0
Pin function
Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and
8-bit timer
channel 1
settings
CKS2
CKS1
CKS0
0
0
DDR select the pin function as follows.
DDR
2
, RxD
7
to CS
2. When an external request is specified as a DMAC activation source,
2
TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR0 are as shown in (1) in the table below.
TEND
, SCK
4
output, input (DREQ
0
2
) by serial communication interface channel 2 (SCI2), and output
output regardless of bits PA
⎯
⎯
0
PA
0
⎯
0
input
(2)
1
, DREQ
0
TEND
TCLKA input*
0
0
Rev.5.00 Sep. 12, 2007 Page 277 of 764
) to the DMA controller (DMAC), input
PA
0
DDR and NDER0.
0
0
output
0
1
output*
15
to TP
3
, TMO
1
1
2
1
8
) from the
(1)
2
, TMIO
TP
REJ09B0396-0500
⎯
1
0
1
output
, TMO
4
1
and CS
7
8. I/O Ports
to CS
0
) by
5
4
in