HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 25

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.4 Usage Notes ...................................................................................................................... 410
Section 12 Watchdog Timer
12.1 Overview........................................................................................................................... 413
12.2 Register Descriptions ........................................................................................................ 415
12.3 Operation........................................................................................................................... 420
12.4 Interrupts ........................................................................................................................... 423
12.5 Usage Notes ...................................................................................................................... 424
Section 13 Serial Communication Interface
13.1 Overview........................................................................................................................... 425
13.2 Register Descriptions ........................................................................................................ 430
11.3.1 Overview.............................................................................................................. 404
11.3.2 Output Timing...................................................................................................... 405
11.3.3 Normal TPC Output............................................................................................. 406
11.3.4 Non-Overlapping TPC Output ............................................................................. 408
11.3.5 TPC Output Triggering by Input Capture ............................................................ 410
11.4.1 Operation of TPC Output Pins ............................................................................. 410
11.4.2 Note on Non-Overlapping Output........................................................................ 411
12.1.1 Features................................................................................................................ 413
12.1.2 Block Diagram ..................................................................................................... 414
12.1.3 Pin Configuration................................................................................................. 414
12.1.4 Register Configuration......................................................................................... 415
12.2.1 Timer Counter (TCNT)........................................................................................ 415
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 416
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 418
12.2.4 Notes on Register Access..................................................................................... 419
12.3.1 Watchdog Timer Operation ................................................................................. 420
12.3.2 Interval Timer Operation ..................................................................................... 422
12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 422
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 423
13.1.1 Features................................................................................................................ 425
13.1.2 Block Diagram ..................................................................................................... 427
13.1.3 Pin Configuration................................................................................................. 428
13.1.4 Register Configuration......................................................................................... 429
13.2.1 Receive Shift Register (RSR) .............................................................................. 430
13.2.2 Receive Data Register (RDR) .............................................................................. 430
13.2.3 Transmit Shift Register (TSR) ............................................................................. 431
13.2.4 Transmit Data Register (TDR)............................................................................. 431
13.2.5 Serial Mode Register (SMR)................................................................................ 432
............................................................................................. 413
................................................................ 425
Rev.5.00 Sep. 12, 2007 Page xxiii of xxviii
REJ09B0396-0500