HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 297

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.7.2
Table 8.11 summarizes the registers of port A.
Table 8.11 Port A Registers
Address*
H'EE009
H'FFFD9
Note:
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Modes
3, 4,
Modes
1, 2
A pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input
port if this bit is cleared to 0. In modes 3 and 4, PA
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 (modes 1 and 2) or H'80 (modes 3 and 4) by a reset and in hardware
standby mode. In software standby mode it retains it previous setting. Therefore, if a transition is
made to software standby mode while a PADDR bit is set to 1, the corresponding pin maintains its
output state.
Bit
* Lower 20 bits of the address in advanced mode.
Initial value
Read/Write
Initial value
Read/Write
Register Configuration
Name
Port A data direction
register
Port A data register
PA DDR
7
⎯
W
7
1
0
PA DDR
6
W
W
6
0
0
PA DDR
Abbreviation
PADDR
PADR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
PA DDR
7
4
DDR is fixed at 1 and PA
W
W
4
0
0
R/W
W
R/W
Rev.5.00 Sep. 12, 2007 Page 267 of 764
PA DDR
3
W
W
3
0
0
Modes 1, 2
H'00
H'00
PA DDR
2
W
W
2
0
0
Initial Value
7
functions as an
PA DDR
REJ09B0396-0500
1
W
W
1
0
0
Modes 3, 4
H'80
H'00
8. I/O Ports
PA DDR
0
W
W
0
0
0