HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 152

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
6.2.7
Bit
Initial value
Read/Write
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface
function, and the access mode, and enables or disables self-refreshing and refresh pin output.
DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5⎯DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are
to function as DRAM interface areas (DRAM space), and at the same time select the RAS output
pin corresponding to each DRAM space.
Bit 7
DRAS2
0
1
Note:
When any of bits DRAS2 to DRAS0 is set to 1, it is not possible to write to DRCRB, RTMCSR,
RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 122 of 764
REJ09B0396-0500
* A single CSn pin serves as a common RAS output pin for a number of areas. Unused
Bit 6
DRAS1
0
1
0
1
DRAM Control Register A (DRCRA)
CSn pins can be used as input/output ports.
DRAS2
Bit 5
DRAS0 Area 5
0
1
0
1
0
1
0
1
R/W
7
0
Normal
Normal
Normal
Normal
Normal
DRAM space
(CS
DRAS1
R/W
5
)
6
0
DRAM space (CS
DRAS0
R/W
5
0
Area 4
Normal
Normal
Normal
Normal
DRAM space
(CS
DRAM space
(CS
4
4
)
)
⎯
⎯
4
1
4
)*
DRAM space (CS
Description
R/W
BE
3
0
Normal
Area 3
Normal
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
3
3
3
)
)
)
2
RDM
R/W
DRAM space (CS
DRAM space (CS
)*
2
0
SRFMD
R/W
Area 2
Normal
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
1
0
2
2
2
2
)
)
)
)
2
2
)*
)*
RFSHE
R/W
0
0