HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 335

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

9.2.7
16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.
Channel
0
1
2
Bit
Initial value
Read/Write
Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source.
The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting
mode and an up-counter in other modes.
16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to
GRA or GRB (counter clearing function).
When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of
the corresponding channel.
When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC
of the corresponding channel.
The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each 16TCNT is initialized to H'0000 by a reset and in standby mode.
Timer Counters (16TCNT)
R/W
15
Abbreviation
16TCNT0
16TCNT1
16TCNT2
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
Function
Up-counter
Phase counting mode: up/down-counter
Other modes: up-counter
R/W
10
0
R/W
9
0
R/W
8
0
R/W
Rev.5.00 Sep. 12, 2007 Page 305 of 764
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
REJ09B0396-0500
R/W
2
0
9. 16-Bit Timer
R/W
1
0
R/W
0
0