HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 538

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

14. Smart Card Interface
2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive
3. Write 0 in the CKE0 bit in SCR to stop the clock.
4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output
5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR).
6. Make the transition to the software standby state.
• Returning from software standby mode to smart card interface mode
1′. Clear the software standby state.
2′. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby
3′. Set smart card interface mode and output the clock. Clock signal generation is started with the
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit to 1 in SCR to start clock output.
Rev.5.00 Sep. 12, 2007 Page 508 of 764
REJ09B0396-0500
operations. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
is fixed at the specified level.
(the current P9
normal duty cycle.
potential.
Figure 14.10 Procedure for Stopping and Restarting the Clock
4
1 2 3
Normal operation
pin state).
4 5 6
Software
standby
1′ 2′ 3′
Normal operation