HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 40

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

1. Overview
Type
System
control
Interrupts NMI
Address
bus
Data bus
Bus
control
Rev.5.00 Sep. 12, 2007 Page 10 of 764
REJ09B0396-0500
Symbol
RES
RESO
STBY
BREQ
BACK
IRQ
IRQ
A
D
CS
CS
AS
RD
HWR
LWR
WAIT
23
15
7
0
to A
to D
5
0
to
to
0
0
FP-100B
TFP-100B FP-100A I/O
63
10
62
59
60
64
17, 16,
90 to 87
100 to 97,
56 to 45,
43 to 36
34 to 23,
21 to 18
2 to 5,
88 to 91
69
70
71
72
58
Pin No.
65
12
64
61
62
66
19, 18,
92 to 89
99, 100,
1, 2,
58 to 47,
45 to 38
36 to 25,
23 to 20
4 to 7,
90 to 93
71
72
73
74
60
Input
Output Reset output: Outputs the reset signal
Input
Input
Output Bus request acknowledge: Indicates that the
Input
Input
Output Address bus: Outputs address signals
Input/
output
Output Chip select: Select signals for areas 7 to 0
Output Address strobe: Goes low to indicate valid
Output Read: Goes low to indicate reading from the
Output High write: Goes low to indicate writing to the
Output Low write: Goes low to indicate writing to the
Input
Name and Function
Reset input: When driven low, this pin resets
the chip.
generated by the watchdog timer to external
devices
Standby: When driven low, this pin forces
a transition to hardware standby mode.
Bus request: Used by an external bus master
to request the bus right
bus has been granted to an external bus
master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable interrupt
request pins
Data bus: Bidirectional data bus
address output on the address bus
external address space
external address space; indicates valid data
on the upper data bus (D
external address space; indicates valid data
on the lower data bus (D
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
7
15
to D
to D
0
).
8
).