HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 13

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Item
10.4.5 Operation with
Cascaded Connection
10.4.6 Input Capture
Setting
11.3.3 Normal TPC
Output
Figure 11.4 Setup
Procedure for Normal
TPC Output (Example)
Figure 11.5 Normal
TPC Output Example
(Five-Phase Pulse
Output)
13.1 Overview
13.2.3 Transmit Shift
Register (TSR)
13.3.4 Synchronous
Operation
Page
373
375
376
406
407
425
431
478
Revision (See Manual for Details)
Description amended
…In this case, the timer operates as below. Similarly, if bits
CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the
8-bit timers of channels 2 and 3 are cascaded. …
Description amended
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter
Note added
Note: When TCORB1 in channel 1 is used for input capture,
Description amended
4. Enable the IMFA interrupt in TISRA.
Description amended
• The 16-bit timer channel to be used as the output trigger
Description amended
The H8/3006 and H8/3007 have a serial communication
interface (SCI) with three independent channels. All three
channels have identical functions. The SCI can communicate in
both asynchronous and synchronous mode. It also has a
multiprocessor communication function for serial
communication among two or more processors.
Description amended
… If the TDRE flag is set to 1 in SSR, however, the SCI does
not load the TDR contents into TSR. The CPU cannot read or
write TSR directly.
Description amended
• The SCI synchronizes with the serial clock input or output and
(8TCNT3) overflows (from H'FF to H'00).
channel is set up so that GRA is an output compare register
and the counter will be cleared by compare match A. The
trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare
match A interrupt.
performs receive operation.
The DMAC can also be set up to transfer data to the next
data register.
TCORB0 in channel 0 cannot be used as a compare
match register.
Similarly, when TCORB3 in channel 3 is used for input
capture, TCORB2 in channel 2 cannot be used as a
compare match register.
Rev.5.00 Sep. 12, 2007 Page xi of xxviii
REJ09B0396-0500