HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 468
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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13. Serial Communication Interface
Bit 4⎯Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
Bit 3⎯Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in
SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
0
1
Note:
Rev.5.00 Sep. 12, 2007 Page 438 of 764
REJ09B0396-0500
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
* The SCI does not transfer receive data from RSR to RDR, does not detect receive
flags retain their previous values.
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives
data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the
MPIE bit to 0, enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to
1), and allows the FER and ORER flags to be set.
Description
Receiving disabled*
Receiving enabled*
Description
Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing conditions]
•
•
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of
the RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
The MPIE bit is cleared to 0
MPB = 1 in received data
2
1
(Initial value)
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