HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 189

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
6. Bus Controller
When RAS down mode is selected, the CAS-before-RAS refresh function provided with this
DRAM interface must always be used as the DRAM refreshing method. When a refresh
operation is performed, the RAS signal goes high immediately beforehand. The refresh
interval setting must be made so that the maximum DRAM RAS pulse width specification is
observed.
When the self-refresh function is used, the RDM bit must be cleared to 0, and RAS up mode
selected, before executing a SLEEP instruction in order to enter software standby mode.
Select RAS down mode again after exiting software standby mode.
Note that RAS down mode cannot be used when HWR and LWR are selected for UCAS and
LCAS, a device other than DRAM is connected to external space, and HWR and LWR are
used as write strobes.
• RAS Up Mode
To select RAS up mode, clear the RDM bit to 0 in DRCRA. Each time access to DRAM space
is interrupted and another space is accessed, the RAS signal returns to the high level. Burst
operation is only performed if DRAM space is continuous. Figure 6.23 shows an example of
the timing in RAS up mode.
External space
DRAM access
DRAM access
access
T
Tr
T
T
T
T
T
T
p
c1
c2
c1
c2
1
2
φ
A
to A
23
0
AS
CSn(RAS)
PB4/PB5
(UCAS/LCAS)
D
to D
15
0
Note: n = 2 to 5
Figure 6.23 Example of Operation Timing in RAS Up Mode
Rev.5.00 Sep. 12, 2007 Page 159 of 764
REJ09B0396-0500

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