HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 210
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 210 of 798
- Download datasheet (5Mb)
6. Bus Controller
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.45.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
Rev.5.00 Sep. 12, 2007 Page 180 of 764
REJ09B0396-0500
(UCAS/LCAS)
Address bus
HWR/LWR
Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
Figure 6.44 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
CSn
φ
(a) Idle cycle not inserted
(DRAM access cycle)
T
p
Bus cycle A
UCAS/LCAS
Address bus
Address bus
T
r
T
c1
Simultaneous change of
HWR/LWR and CSn
RD
T
φ
c2
Bus cycle B
T
1
T
External read
1
T
2
T
2
(UCAS/LCAS)
T
Address bus
3
HWR/LWR
T
DRAM space read
p
CSn
T
φ
r
(DRAM access cycle) Bus cycle B
T
T
c1
Bus cycle A
p
(b) Idle cycle inserted
T
T
r
c2
T
c1
T
c2
T
i
T
1
T
2
Related parts for HD6413007F20
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT STARTER FOR M16C/29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/2D
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
R0K33062P STARTER KIT
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/23 E8A
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/25
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER H8S2456 SHARPE DSPLY
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C38C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C35C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8CL3AC+LCD APPS
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR RX610
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R32C/118
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV RSK-R8C/26-29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR SH7124
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR H8SX/1622
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV FOR SH7203
Manufacturer:
Renesas Electronics America
Datasheet: