HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 250

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7. DMA Controller
Figure 7.9 shows a sample setup procedure for normal mode.
Rev.5.00 Sep. 12, 2007 Page 220 of 764
REJ09B0396-0500
Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU.
Set initial destination address
Set initial source address
Set transfer count
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Set DTCRB (1)
Set DTCRA (1)
Set DTCRB (2)
Set DTCRA (2)
Read DTCRB
Read DTCRA
Normal mode
Normal mode
Figure 7.9 Normal Mode Setup Procedure (Example)
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2
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5
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8
9
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7.
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9.
Set the initial source address in MARA.
Set the initial destination address in MARB.
Set the transfer count in ETCRA.
Set the DTCRB bits as follows.
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Set the DTCRA bits as follows.
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Read DTCRB with DTME cleared to 0.
Set the DTME bit to 1 in DTCRB.
Read DTCRA with DTE cleared to 0.
Set the DTE bit to 1 in DTCRA to enable the transfer.
Clear the DTME bit to 0.
Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
Select the DMAC activation source with bits
DTS2B to DTS0B.
Clear the DTE bit to 0.
Select byte or word size with the DTSZ bit.
Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
Clear the DTS0A bit to 0 and set the DTS2A
and DTS1A bits to 1 to select normal mode.