HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 393

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
Bit 4⎯A/D Trigger Enable (ADTE) (8TCSR0): In combination with TRGE in the A/D control
register (ADCR), enables or disables A/D converter start requests by compare match A or an
external trigger. Bit 4 of 8TCSR2 is reserved, but can be read and written.
TRGE*
0
1
Note:
Bit 4⎯Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written.
Bit 4⎯Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of
TCORB1 and TCORB3.
Bit 4
ICE
0
1
When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB
registers in channels 0 to 3 is as shown in the tables below.
* TRGE is bit 7 of the A/D control register (ADCR).
Bit 4
ADTE
0
1
0
1
Description
TCORB1 and TCORB3 are compare match registers
TCORB1 and TCORB3 are input capture registers
Description
A/D converter start requests by compare match A or an external trigger pin
(ADTRG) input are disabled
A/D converter start requests by compare match A or an external trigger pin
(ADTRG) input are disabled
A/D converter start requests by an external trigger pin (ADTRG) are enabled,
and A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and A/D
converter start requests by an external trigger pin (ADTRG) are disabled
Rev.5.00 Sep. 12, 2007 Page 363 of 764
REJ09B0396-0500
10. 8-Bit Timers
(Initial value)
(Initial value)

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