HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 20

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10 Bus Arbiter........................................................................................................................ 182
6.11 Register and Pin Input Timing .......................................................................................... 185
Rev.5.00 Sep. 12, 2007 Page xviii of xxviii
REJ09B0396-0500
Operation .......................................................................................................................... 130
6.3.1
6.3.2
6.3.3
6.3.4
Basic Bus Interface ........................................................................................................... 134
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
DRAM Interface ............................................................................................................... 147
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 154
6.5.11 Refresh Control.................................................................................................... 160
6.5.12 Examples of Use .................................................................................................. 164
6.5.13 Usage Notes ......................................................................................................... 168
Interval Timer ................................................................................................................... 170
6.6.1
Interrupt Sources............................................................................................................... 175
Burst ROM Interface......................................................................................................... 176
6.8.1
6.8.2
6.8.3
Idle Cycle.......................................................................................................................... 178
6.9.1
6.9.2
6.10.1 Operation ............................................................................................................. 182
6.11.1 Register Write Timing ......................................................................................... 185
Area Division....................................................................................................... 130
Bus Specifications................................................................................................ 132
Memory Interfaces............................................................................................... 133
Chip Select Signals .............................................................................................. 133
Overview.............................................................................................................. 134
Data Size and Data Alignment............................................................................. 134
Valid Strobes........................................................................................................ 136
Memory Areas ..................................................................................................... 136
Basic Bus Control Signal Timing ........................................................................ 138
Wait Control ........................................................................................................ 145
Overview.............................................................................................................. 147
DRAM Space and RAS Output Pin Settings ....................................................... 147
Address Multiplexing........................................................................................... 148
Data Bus............................................................................................................... 148
Pins Used for DRAM Interface............................................................................ 149
Basic Timing........................................................................................................ 149
Precharge State Control ....................................................................................... 151
Wait Control ........................................................................................................ 152
Byte Access Control and CAS Output Pin........................................................... 153
Operation ............................................................................................................. 170
Overview.............................................................................................................. 176
Basic Timing........................................................................................................ 176
Wait Control ........................................................................................................ 177
Operation ............................................................................................................. 178
Pin States in Idle Cycle ........................................................................................ 181