HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 484

IC H8 MCU ROMLESS 5V 100QFP

HD6413007F20

Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413007F20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413007F20V
Manufacturer:
RENESAS-Pb free
Quantity:
2
13. Serial Communication Interface
Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
φ (MHz)
2
4
6
8
10
12
14
16
18
20
13.3
13.3.1
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses. A smart card interface is also supported as a serial
communication function for an IC card interface.
Selection of asynchronous or synchronous mode and the transmission format for the normal serial
communication interface is made in SMR, as shown in table 13.8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9.
For details of the procedures for switching between LSB-first and MSB-first mode and inverting
the data logic level, see section 14.2.1, Smart Card Mode Register (SCMR).
For selection of the smart card interface format, see section 14.3.3, Data Format.
Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
Rev.5.00 Sep. 12, 2007 Page 454 of 764
REJ09B0396-0500
selections determine the communication format and character length.
state.
Operation
Overview
External Input Clock (MHz)
0.3333
0.6667
1.0000
1.3333
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
Maximum Bit Rate (bit/s)
333333.3
666666.7
1000000.0
1333333.3
1666666.7
2000000.0
2333333.3
2666666.7
3000000.0
3333333.3

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