HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 546

• Manufacturer Part Number: HD6413007F20
• Description: IC H8 MCU ROMLESS 5V 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413007F20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

15. A/D Converter
15.1.4
Table 15.2 summarizes the A/D converter's registers.
Table 15.2 A/D Converter Registers
H'FFFE0
H'FFFE1
H'FFFE2
H'FFFE3
H'FFFE4
H'FFFE5
H'FFFE6
H'FFFE7
H'FFFE8
H'FFFE9
Notes: 1. Lower 20 bits of the address in advanced mode.
15.2
15.2.1
Bit
ADDRn
Initial value
Read/Write
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
Rev.5.00 Sep. 12, 2007 Page 516 of 764
REJ09B0396-0500
Address*
2. Only 0 can be written in bit 7, to clear the flag.
Register Descriptions
Register Configuration
A/D Data Registers A to D (ADDRA to ADDRD)
1
AD9
15
A/D data register AH
A/D data register AL
A/D data register BH
A/D data register BL
A/D data register CH
A/D data register CL
A/D data register DH
A/D data register DL
A/D control/status register
A/D control register
Name
R
0
AD8
14
R
0
AD7
13
R
0
A/D conversion data
10-bit data giving an
A/D conversion result
AD6
12
R
0
AD5
11
R
0
AD4
10
R
0
AD3
R
9
0
AD2
R
8
0
AD1
R
7
0
ADDRAH
ADDRAL
ADDRBH
ADDRBL
ADDRCH
ADDRCL
ADDRDH
ADDRDL
ADCSR
ADCR
Abbreviation
AD0
R
6
0
⎯
R
5
0
⎯
R
4
0
Reserved bits
R
R
R
R
R
R
R
R
R/(W)*
R/W
R/W
⎯
R
3
0
⎯
2
R
2
0
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'7E
Initial Value
⎯
R
1
0
⎯
R
0
0