NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 816

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Table 23-23. Power Management Timings (Sheet 3 of 3)
816
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
2. If the AFTERG3_EN bit (GEN_PMCON_3 Configuration Register Bit 1) is set to a 1, SLP_S5# will not be de-
3. The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the
4. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 28.992 µs to 32.044 µs.
5. Note that this does not apply for synchronous SMIs.
6. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
7. This is a clock generator specification.
8. This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert time for DPRSLPVR
9. This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert time for STP_CPU#
10.This value should be at most a few clocks greater than the minimum.
11.This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 µs).
12.The ICH7 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing for
13.The ICH7 has no maximum timing requirement for this transition. It is up to the system designer to determine
14.t290, t293, and t294 apply during S0 to G3 transitions only. In addition, the timings are not applied to V5REF.
15.A Vcc supply is inactive when the voltage is below the min value specified in
16.If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together
17.t303 applies during S0 to S3-S5 transitions.
18.RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.1 V.
NOTES:
Sym
t298
t299
t300
t301
t302
t303
t310
t311
t312
RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
asserted until a wake event is detected. If the AFTERG3_EN bit is set to 0, SLP_S5# will deassert within the
specification listed in the table.
“SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).
has been met, then this is permitted to be 0.
has been met, then this is permitted to be 0.
this cycle getting to the ICH7 is dependant on the processor and the memory controller.
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
V5REF timings are bonded by power sequencing.
similar to timing t287 (PCIRST# active to SLP_S3# active).
SLP_S4# inactive to SLP_S3# inactive
S4 Wake Event to SLP_S4# inactive (S4
Wake)
S3 Wake Event to SLP_S3# inactive (S3
Wake)
CPUSLP# inactive to STPCLK# inactive
(Desktop Only)
SLP_S3# inactive to ICH7 check for PWROK
active
SLP_S3# active to Vcc supplies inactive
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
RSMRST# rising edge transition from 20% to 80%
RSMRST# falling edge transition
Parameter
Other Timings
Min
1
0
8
4
5
See Note Below
small
possi
Max
ble
50
as
2
5
3
Intel
Table
RTCCLK
RTCCLK
PCI CLK
PCICLK
Units
msec
us
us
®
Electrical Characteristics
23-8.
ICH7 Family Datasheet
Notes
15, 17
18
4
3
4
23-23
23-24
23-25
23-26
23-23
23-24
23-25
23-26
23-23
23-24
23-25
23-26
23-22
23-23
23-24
23-25
23-26
Fig