NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 614

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

15.1.26
15.1.27
614
ATC—APM Trapping Control Register (IDE—D31:F1)
Address Offset: C0h
Default Value:
ATS—APM Trapping Status Register (IDE—D31:F1)
Address Offset: C4h
Default Value:
7:2
7:2
Bit
Bit
1
0
1
0
Reserved
Slave Trap (PST) — R/W.
0 = Disable.
1 = Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h–1F7h and
Master Trap (PMT) — R/W.
0 = Disable.
1 = Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h–1F7h and
Reserved
Slave Trap Status (PSTS) — R/WC.
1 = Trap occurred to the slave device
Master Trap Status (PMTS) — R/WC.
0 = Trap occurred to the master device
3F6h. The active device must be the slave device for the trap and/or SMI# to occur.
3F6h. The active device must be master device for the trap and/or SMI# to occur.
00h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
IDE Controller Registers (D31:F1)
Intel
R/W
8 bits
R/WC
8 bits
®
ICH7 Family Datasheet