NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 717

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NH82801GHM S L8YR

Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801GHM S L8YR

Lead Free Status / RoHS Status
Compliant
Intel® High Definition Audio Controller Registers (D27:F0)
19.1.25
Intel
®
ICH7 Family Datasheet
PCS—Power Management Control and Status Register
(Intel
Address Offset: 54h–57h
Default Value:
31:24
21:16
14:9
7:2
1:0
Bit
23
22
15
8
Data — RO. Does not apply. Hardwired to 0.
Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.
B2/B3 Support — RO. Does not apply. Hardwired to 0.
Reserved.
PME Status (PMES) — R/WC.
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel
This bit is in the resume well and only cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
Reserved
PME Enable (PMEE) — R/W.
0 = Disable
1 = when set and if corresponding PMES also set, the Intel High Definition Audio
This bit is in the resume well and only cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
Reserved
Power State (PS) — R/W. This field is used both to determine the current power state
of the Intel High Definition Audio controller and to set a new power state.
00 = D0 state
11 = D3
Others = reserved
NOTES:
1.
2.
3.
®
High Definition Audio Controller—D27:F0)
assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this
register)
controller sets the AC97_STS bit in the GPE0_STS register (PMBASE +28h). The
AC97_STS bit is shared by AC ’97 and Intel High Definition Audio functions since
they are mutually exclusive.
If software attempts to write a value of 01b or 10b in to this field, the write
operation must complete normally; however, the data is discarded and no state
change occurs.
When in the D3
configuration space is available, but the I/O and memory space are not.
Additionally, interrupts are blocked.
When software changes this value from D3
warm (soft) reset is generated, and software must re-initialize the function.
HOT
00000000h
state
HOT
states, the Intel High Definition Audio controller’s
®
High Definition Audio controller would normally
Description
Attribute:
Size:
HOT
state to the D0 state, an internal
RO, R/W, R/WC
32 bits
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